This project is to design a AXI4 DMA test program for the Xilinx Zynq UltraScale board to test maximum transmit speed from PL to DDR4 in PS via HP. Transmitted data from one data source port generated in PL, it is sent from PL to PS, and is saved in DDR4 as a block of data finally. The minimum speed should not be lower than 4GB/s ( 32Gbps). And the transmitted data shouldn’t less than 200MB. which we have tested can be over 60 Gbps using three HPs under bare machine mode, we can help you optimize the SG parameters to get a high speed, but your code needs support send data (more than 200 MB) continuously.
The AXI4-DMA SG (scatter gather) mode supports a maximum transmission 64 M bit one time.
Softwave platform: Xilinx vivado using petalinux vivado 2018.
Hardwave platform: Xilinx Zcu106 or other xilinx borad supporting vivado.
The development time: no more than one week.
Note: 1) The program need to be developed under AXI4-DMA SG (scatter gather) mode in petalinux.
2)To achieve high speed, the SG mode cann't use send data once,and then stop, initialize device, and transmit again, which take up too much time to reduce speed.
3) the project needs three HPs to achieve speed over 40 Gbps, I can help you optimize the parameters of DMA and HP.
4) when multiple HPs are used, the device tree needs to be considered how to set up to ensure that DMAs are feasible.
Submission contents: source codes and implementation instructions to help verify the performance of the code.