Matlab codes porting to FPGA

The FPGA project is to porting a WLAN’s PHY cores into a Xilinx FPGA development board (E.g Spartan 3A). Use of the public domain WLAN’s PHY cores from Rice University’s WARP project (http://warp.rice.edu/trac/wiki/OFDMReferenceDesign/Changelog), the cores (Matlab Simulink’s mdl files) porting into a Xilinx FPGA development board. We recommend to goto the rice.edu link (above), download the matlab files, and try out yourself first before your bid.

Details Project Tasks are followings;

•Break the WARP’s Simulink’s mdl files into transmitter (Tx) and receiver (Rx) parts (currently, the WARP mdl files are combined) because the core logics are too big for the Spartan3A chip, and port the each part into a Xilinx’s Spartan3A-DSP board.
•Perform a slight modification and adding for the WARP mdl files to fit the board and demonstration (will be discussed later).
•The Xilinx’s Spartan3A-DSP board is combined with a P160 Analog-to-Digital daughter card (ADC/DAC) by Avnet. The WARP Simulink mdl and P160 ADC Simulink mdl files are need to integrate together for TX and RX.
•A simple Matlab GUI will design for configure and run the board.

Qualifications for this project;

•Must familiar with Xilinx FPGA design tools including System Generator, and required experience for porting/debug on various Xilinx development boards.
•Must familiar with Matlab and Simulink
•Must familiar with WLAN technology (OFDM modulation/demodulation), DSP
•Experience on DSO, Spectrum analyzer, ADC/DAC board, hands-on digital signal processing, and data analysis.

If you are interested to submit this project, we encourage to download the WARP project and try first before you bid. And submit precise technical details that how you can divide the cores into TX/RX. And expect to have multiple technical discussions before we finalize the project contract.