Multi-Cycle Processor Design
Budget: $30 – $250 USD
You are to design and implement a multi-cycle processor with the following specifications.
The accumulator-based processor has a 16-bit data bus and a 13-bit address bus. This CPU
has 8 instructions that are shown in Table 1. Each instruction is 16 bits wide and occupies
a memory word. As shown in Table 1, instructions have a 3-bit opcode field. The remaining
13 bits of instructions form the address field. The instruction format is shown in Figure 1.
A) Design and implement the datapath and controller of this multi-cycle CPU and Show
the schematics.
B) Write complete Verilog code and a testbench and run the simulation.
The accumulator-based processor has a 16-bit data bus and a 13-bit address bus. This CPU
has 8 instructions that are shown in Table 1. Each instruction is 16 bits wide and occupies
a memory word. As shown in Table 1, instructions have a 3-bit opcode field. The remaining
13 bits of instructions form the address field. The instruction format is shown in Figure 1.
A) Design and implement the datapath and controller of this multi-cycle CPU and Show
the schematics.
B) Write complete Verilog code and a testbench and run the simulation.